? semiconductor components industries, llc, 2002 january, 2002 rev. 7 1 publication order number: mc10188/d mc10188 hex buffer with enable the mc10188 is a highspeed hex buffer with a common enable input. when enable is in the high state, all outputs are in the low state. when enable is in the low state, the outputs take the same state as the inputs. ? power dissipation = 180 mw typ/pkg (no load) ? propagation delay = 2.0 ns typ (b q) 2.5 ns typ (a q) dip pin assignment v cc1 a out b out c out a in b in c in v ee v cc2 f out e out d out f in e in d in common 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 pin assignment is for dualinline package. for plcc pin assignment, see the pin conversion tables on page 18 of the on semiconductor mecl data book (dl122/d). logic diagram v cc1 = pin 1 v cc2 = pin 16 v ee = pin 8 12 15 11 14 10 13 7 4 6 3 5 2 9 x y out truth table inputs output x y out l l l l h h h l l h h l http://onsemi.com device package shipping ordering information mc10188l cdip16 25 units / rail mc10188p pdip16 25 units / rail mc10188fn plcc20 46 units / rail marking diagrams 1 16 a = assembly location wl = wafer lot yy = year ww = work week cdip16 l suffix case 620 mc10188l awlyyww pdip16 p suffix case 648 plcc20 fn suffix case 775 10188 awlyyww 1 1 16 mc10188p awlyyww
mc10188 http://onsemi.com 2 electrical characteristics test limits pin under 30 c +25 c +85 c characteristic symbol u n d er test min max min max min max unit power supply drain current i e 8 46 42 46 madc input current i inh 5 425 265 265 m adc i inh 9 460 290 290 m adc output voltage logic 1 v oh 2 1.060 0.890 0.960 0.810 0.890 0.700 vdc output voltage logic 0 v ol 2 1.890 1.675 1.850 1.650 1.825 1.615 vdc threshold voltage logic 1 v oha 2 1.080 0.980 0.910 vdc threshold voltage logic 0 v ola 2 1.655 1.630 1.595 vdc switching times (50 w load) ns propagation delay enable data t phl t plh 2 2 1.1 1.0 3.9 3.3 1.1 1.0 3.5 2.9 1.1 1.0 3.9 3.3 rise/fall time (20 to 80%) t tlh t thl 2 1.1 3.7 1.1 3.3 1.1 3.7 electrical characteristics (continued) test voltage values (volts) @ test temperature v ihmax v ilmin v ihamin v ilamax v ee 30 c 0.890 1.890 1.205 1.500 5.2 +25 c 0.810 1.850 1.105 1.475 5.2 +85 c 0.700 1.825 1.035 1.440 5.2 pin under test voltage applied to pins listed below (v ) characteristic symbol under test v ihmax v ilmin v ihamin v ilamax v ee (v cc ) gnd power supply drain current i e 8 8 1, 16 input current i inh 5 5 8 1, 16 i inh 9 9 8 1, 16 output voltage logic 1 v oh 2 5 8 1, 16 output voltage logic 0 v ol 2 9 8 1, 16 threshold voltage logic 1 v oha 2 5 8 1, 16 threshold voltage logic 0 v ola 2 5 8 1, 16 switching times (50 w load) pulse in pulse out 3.2 v +2.0 v propagation delay enable data t phl t plh 2 2 9 5 2 2 8 8 1, 16 1, 16 rise/fall time (20 to 80%) t tlh t thl 2 5 2 8 1, 16 each mecl 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibr ium has been established. the circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is ma intained. outputs are terminated through a 50ohm resistor to 2.0 volts. test procedures are shown for only one gate. the other gates are tested in the same manner.
mc10188 http://onsemi.com 3 package dimensions plcc20 fn suffix plastic plcc package case 77502 issue c notes: 1. datums -l-, -m-, and -n- determined where top of lead shoulder exits plastic body at mold parting line. 2. dimension g1, true position to be measured at datum -t-, seating plane. 3. dimensions r and u do not include mold flash. allowable mold flash is 0.010 (0.250) per side. 4. dimensioning and tolerancing per ansi y14.5m, 1982. 5. controlling dimension: inch. 6. the package top may be smaller than the package bottom by up to 0.012 (0.300). dimensions r and u are determined at the outermost extremes of the plastic body exclusive of mold flash, tie bar burrs, gate burrs and interlead flash, but including any mismatch between the top and bottom of the plastic body. 7. dimension h does not include dambar protrusion or intrusion. the dambar protrusion(s) shall not cause the h dimension to be greater than 0.037 (0.940). the dambar intrusion(s) shall not cause the h dimension to be smaller than 0.025 (0.635). m n l y brk w v d d s l-m m 0.007 (0.180) n s t s l-m m 0.007 (0.180) n s t s l-m s 0.010 (0.250) n s t x g1 b u z view dd 20 1 s l-m m 0.007 (0.180) n s t s l-m m 0.007 (0.180) n s t s l-m s 0.010 (0.250) n s t c g view s e j r z a 0.004 (0.100) t seating plane s l-m m 0.007 (0.180) n s t s l-m m 0.007 (0.180) n s t h view s k k1 f g1 dim min max min max millimeters inches a 0.385 0.395 9.78 10.03 b 0.385 0.395 9.78 10.03 c 0.165 0.180 4.20 4.57 e 0.090 0.110 2.29 2.79 f 0.013 0.019 0.33 0.48 g 0.050 bsc 1.27 bsc h 0.026 0.032 0.66 0.81 j 0.020 --- 0.51 --- k 0.025 --- 0.64 --- r 0.350 0.356 8.89 9.04 u 0.350 0.356 8.89 9.04 v 0.042 0.048 1.07 1.21 w 0.042 0.048 1.07 1.21 x 0.042 0.056 1.07 1.42 y --- 0.020 --- 0.50 z 2 10 2 10 g1 0.310 0.330 7.88 8.38 k1 0.040 --- 1.02 ---
mc10188 http://onsemi.com 4 cdip16 l suffix ceramic dip package case 62010 issue t notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension l to center of lead when formed parallel. 4. dimension f may narrow to 0.76 (0.030) where the lead enters the ceramic body. a b t f e g n k c seating plane 16 pl d s a m 0.25 (0.010) t 16 pl j s b m 0.25 (0.010) t m l dim min max min max millimeters inches a 0.750 0.785 19.05 19.93 b 0.240 0.295 6.10 7.49 c --- 0.200 --- 5.08 d 0.015 0.020 0.39 0.50 e 0.050 bsc 1.27 bsc f 0.055 0.065 1.40 1.65 g 0.100 bsc 2.54 bsc h 0.008 0.015 0.21 0.38 k 0.125 0.170 3.18 4.31 l 0.300 bsc 7.62 bsc m 0 15 0 15 n 0.020 0.040 0.51 1.01 16 9 18 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension l to center of leads when formed parallel. 4. dimension b does not include mold flash. 5. rounded corners optional. a b f c s h g d j l m 16 pl seating 18 9 16 k plane t m a m 0.25 (0.010) t dim min max min max millimeters inches a 0.740 0.770 18.80 19.55 b 0.250 0.270 6.35 6.85 c 0.145 0.175 3.69 4.44 d 0.015 0.021 0.39 0.53 f 0.040 0.70 1.02 1.77 g 0.100 bsc 2.54 bsc h 0.050 bsc 1.27 bsc j 0.008 0.015 0.21 0.38 k 0.110 0.130 2.80 3.30 l 0.295 0.305 7.50 7.74 m 0 10 0 10 s 0.020 0.040 0.51 1.01 pdip16 p suffix plastic dip package case 64808 issue r on semiconductor and are trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scill c data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthori zed use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. publication ordering information japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402700 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. mc10188/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com n. american technical support : 8002829855 toll free usa/canada
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